PERFORMANCE AND ANALYSIS OF LOW POWER, AREAEFFICIENT AND HIGH SPEED CARRYFAST ADDER

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International Journal on Smart Sensing and Intelligent Systems

Professor Subhas Chandra Mukhopadhyay

Exeley Inc. (New York)

Subject: Computational Science & Engineering , Engineering, Electrical & Electronic

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VOLUME 10 , ISSUE 5 (December 2017) > List of articles

Special Issue

PERFORMANCE AND ANALYSIS OF LOW POWER, AREAEFFICIENT AND HIGH SPEED CARRYFAST ADDER

M. AntoBennet * / S. Sankaranarayanan / V. BanuPriya / PJaya Pretheena / S. Yamini / S. Supriya

Keywords : Carry Select Adder (CSLA), Binary to Excess-1 Converter (BEC), Carry-propagation adder (CPA)

Citation Information : International Journal on Smart Sensing and Intelligent Systems. Volume 10, Issue 5, Pages 0-0, DOI: https://doi.org/10.21307/ijssis-2017-268

License : (CC BY-NC-ND 4.0)

Received Date : 27-May-2017 / Accepted: 15-June-2017 / Published Online: 01-September-2017

ARTICLE

ABSTRACT

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8, 16,32,and 64-bit square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power. Binary to Excess-1 Converter (BEC) instead of RCA with the regular CSLA to achieve lower area and power consumption. The main advantage of this BEC logic comes from the lesser number of logic gates than the n-bit Full Adder structure. The delay and area evaluation methodology of the basic adder blocks. The SQRT CSLA has been chosen for comparison with the proposed design as it has a more balanced delay, and requires lower power and area. Reducing the area and power consumption in the CSLA. Efficient gate-level modification to significantly reduce the area and powerof the CSLA.

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