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International Journal on Smart Sensing and Intelligent Systems

Professor Subhas Chandra Mukhopadhyay

Exeley Inc. (New York)

Subject: Computational Science & Engineering , Engineering, Electrical & Electronic


eISSN: 1178-5608



VOLUME 2 , ISSUE 4 (December 2009) > List of articles


Shubhajit Roy Chowdhury * / Dipankar Mukherjee * / Hiranmay Saha *

Citation Information : International Journal on Smart Sensing and Intelligent Systems. Volume 2, Issue 4, Pages 661-675, DOI: https://doi.org/10.21307/ijssis-2017-374

License : (CC BY-NC-ND 4.0)

Published Online: 03-November-2017



The paper presents a Field Programmable Gate Array (FPGA) based tracker to accurately track the maximum power point (MPP) of a photovoltaic (PV) array. The tracking logic realized on FPGA is based on a modified version of Adaptive Perceptive Particle Swarm Optimization (APPSO) technique. Photovoltaic generation systems use MPP tracker because the photovoltaic array exhibits multiple maxima in the power voltage characteristic under partially shaded conditions. Compared to PSO, the APPSO offers flexibility in the motion dynamics of the particle in the search space through variation in perception radius, number of sampling points per directions, and the number of sampling directions. The APPSO algorithm has been suitably modified to suit to the slight changes in the maximum power point at around the maximum power point. The proposed technique uses only one pair of sensors to control multiple PV arrays. This results in lower cost, higher accuracy and also the algorithm is simple. The implementation of the algorithm on a reconfigurable architecture like FPGA ensures hardware based flexibility in the motion dynamics presented by APPSO. A comparative study is performed to compare the performance of PSO and APPSO with respect to MPP tracking. Compared to PSO that track to the MPP under partial shading conditions and reaches the MPP with 96.41% accuracy, the APPSO can track to the MPP with 97.95% accuracy. The algorithm when realized on an Altera Cyclone EP1C6Q240C8 FPGA consumes 5967 logic blocks.

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