Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors


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International Journal on Smart Sensing and Intelligent Systems

Professor Subhas Chandra Mukhopadhyay

Exeley Inc. (New York)

Subject: Computational Science & Engineering, Engineering, Electrical & Electronic


eISSN: 1178-5608



VOLUME 4 , ISSUE 2 (June 2011) > List of articles

Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors

P. Saha / A. Banerjee / A. Dandapat / P. Bhattacharyya *

Keywords : Vedic Formulae, Multiplication, High Speed, Low Power, Latency.

Citation Information : International Journal on Smart Sensing and Intelligent Systems. Volume 4, Issue 2, Pages 268-284, DOI:

License : (CC BY-NC-ND 4.0)

Received Date : 09-May-2011 / Accepted: 25-May-2011 / Published Online: 01-June-2011



Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique for arithmetic computations based on 16 Sutras (Formulae). Transistor level implementation (ASIC) of Vedic Mathematics based 32-bit multiplier for high speed low power processor is reported in this paper. Simple Boolean logic is combined with ‘Vedic’ formulas, which reduces the partial products and sums generated in one step, reduces the carry propagation from LSB to MSB. The implementation methodology ensure substantial reduction of propagation delay in comparison with Wallace Tree (WTM), modified Booth Algorithm (MBA), Baugh Wooley (BWM) and Row Bypassing and Parallel Architecture (RBPA) based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting 32×32 multiplier was only ~1.06 us and consumes ~132 uW power. The implementation offered significant improvement in terms of delay and power from earlier reported ones.

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[1] A. Asati and Chandrashekhar, “An Improved High Speed fully pipelined 500 MHz 8×8 Baugh Wooley Multiplier design using 0.6 μm CMOS TSPC Logic Design Style”, Proc. IEEE, ICIINFS 2008, pp. 1-6, Dec. 8-10, 2008.
[2] A. Chandrakasan and R. Brodersen, “Low-power CMOS digital design” , IEEE Journals on Solid-State Circuits, Vol. 27, No. 4, pp. 473–484, Apr. 1992.
[3 ] N.-Y. Shen and O. T.-C. Chen, “Low-power multipliers by minimizing switching activities of partial products”, Proc. IEEE, ISCAS 2002, vol. 4, pp. 93–96, May 2002.
[4] O. T. Chen, S. Wang, and Y.-W. Wu, “Minimization of switching activities of partial products for designing low-power multipliers,” IEEE Transc. on Very Large Scale Integration (VLSI) Syst., Vol. 11, No. 3, pp. 418–433, June 2003.
[4] B. Parhami, Computer Arithmetic Algorithms and Hardware Designs, 1st ed. Oxford, U.K.: Oxford Univ. Press, 2000.
[5] C. S Wallace, “A Suggestion for a Fast Multiplier,” IEEE Trans. on Computers, Vol. EC13, pp. 14-17, December 1964.
[6] J. Hu, L. Wang, and T. Xu, “A Low-Power Adiabatic Multiplier Based on Modified Booth Algorithm”, Proc. IEEE, ISIC’07, pp. 489-492, Sept. 26-28, 2007.
[7] C. R. Baugh, and B.A. Wooley, “A Two's Complement Parallel Array Multiplication Algorithm”, IEEE transc. on Computers, Vol. C-22, No. 12, pp. 1045-1047, December 1973
[8] K-C. Kuo, and C-W. Chou, “Low power and high speed multiplier design with row bypassing and parallel architecture, Journal of Microelectronics, 2010, doi:10.1016/j.mejo.2010.06.009
[9] K. Z. Pekmestzi, “Multiplexer-Based Array Multipliers”, IEEE transc. on Computers, Vol 48, No. 1, pp. 15-23, January 1999.
[10] [11] P. K. Saha, A. Banerjee, and A. Dandapat, “High Speed Low Power Complex Multiplier Design Using Parallel Adders and Subtractors”, International Journal on Electronic and Electrical Engineering, (IJEEE), vol 07, no. 11, pp 38-46, December 2009.
[11] Z. Huang, and M. D. Ercegovac, “High-Performance Low-Power Left-to-Right Array Multiplier Design,” IEEE Transactions on Computers, vol 54, no. 3, pp 272-283, March 2005.
[12] P.-M. Seidel, L.D. McFearin and D.W. Matula, “Secondary radix recodings for higher radix multipliers”, IEEE transc. on Computers, Vol 54, No. 2, pp. 111- 123, February 2005.
[13] P. Mehta, and D. Gawali, “Conventional versus Vedic mathematical method for Hardware implementation of a multiplier,” Proc. IEEE ACT-2009, pp. 640-642, Dec. 28-29, 2009.
[14] H. D. Tiwari, G. Gankhuyag, C. M. Kim, and Y. B. Cho, “Multiplier design based on ancient Indian Vedic Mathematics,” Proc. IEEE International SoC Design Conference, pp. 65-68, Nov. 24-25, 2008.
[15] P. Saha, A. Banerjee, P. Bhattacharyya, and A. Dandapat, “High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics”, Proc. (Abstract) IEEE TechSym 2011, pp. 38-38,Jan 14-16.
[16] P. K. Saha, A. Banerjee, and A. Dandapat, “High Speed Low Power Factorial Design in 22nm Technology,” Proc. AIP2009, pp. 294-301, 2009.