Design of high precision time synchronization system based on GPS/BD dual mode

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International Journal of Advanced Network, Monitoring and Controls

Xi'an Technological University

Subject: Computer Science , Software Engineering

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eISSN: 2470-8038

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VOLUME 1 , ISSUE 2 (December 2016) > List of articles

Design of high precision time synchronization system based on GPS/BD dual mode

YU Fan / MA Xing / Wang Zhongsheng

Keywords : GPS/BD dual-mode, time synchronization, PLL; unbiased FIR filter

Citation Information : International Journal of Advanced Network, Monitoring and Controls. Volume 1, Issue 2, Pages 89-95, DOI: https://doi.org/10.2991/mcei-16.2016.231

License : (CC BY 4.0)

Published Online: 08-April-2018

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ABSTRACT

In this paper, a new method of clock disciplining based on GPS/BD dual-mode receiver is proposed, which can improve the estimation accuracy of clock bias by fusing the GPS clock bias data and the BD clock bias data. In addition, the use of unbiased FIR filtering algorithm to filter the clock bias data to improve the accuracy of the clock filter. According to the experimental results, the time synchronization precision of the proposed method is 50ns, which is better than that based on single mode GPS and single mode BD time synchronization system.

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SHAN Qingxiao, YANG Jun. Review of satellite Disciplined Colck System[J], Journal of Test and Measurement Technology, 2009,235:397-400.

 

M. R. Mosavi. Use of Accurate GPS Timing based on Radial Basis Probabilistic Neural Network in Electric Systems[C]. International Conference on Electrical and Control Engineering20102572-2575.

 

Xie Qiang, Qian Guangdi. Design and realization of high precise frequency source based on timing GPS[J], Industrial Control Computer, 2007, 203: 15-16.

 

Beomsup Kim. Dual-loop DPLL gear-shifting algorithm for fast synchronization [ J] . IEEE Transactions on Circuits and Systems-II : Analog and Digital Signal Processing, 1997, 44( 7): 577.

 

Shmaliy Y S. An unbiased FIR filter for TIE model of a local clock in applications to GPS-based timekeeping[J]. ieee transactions on ultrasonics, ferroelectrics, and frequency control, 2006, 53(5): 862-870.

 

Shmaliy.S Y, Munoz-Diaz J, Arceo-Miquel L, et al. Optimum time step and memory for GPS-based unbiased FIR estimates of the local clock TIE model[C]. IEEE International Frequency Control Symposium Jointly with the 21st European Frequency and Time Forum, 2007, 291-296.

 

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