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  • In Jour Smart Sensing And Intelligent Systems

 

Research Article

On Evolution of CMOS Image Sensors

CMOS Image Sensors have become the principal technology in majority of digital cameras. They started replacing the film and Charge Coupled Devices in the last decade with the promise of lower cost, lower power requirement, higher integration and the potential of focal plane processing. However, the principal factor behind their success has been the ability to utilise the shrinkage in CMOS technology to make smaller pixels, and thereby have more resolution without increasing the cost. With the

Luiz Carlos Paiva Gouveia, Bhaskar Choubey

International Journal on Smart Sensing and Intelligent Systems , ISSUE 5, 1–6

Article

Thermal Effects in Design of Integrated CMOS MEMS High Resolution Pressure Sensor

Thermal effects in integrated piezoresistive MEMS pressure sensor may be a problem of concern in design for applications requiring high precision measurements and in continuously monitoring array of sensor network. It not only results in the shift of the offset voltage of the pressure sensor but also affects the performance of the adjacent CMOS circuit leading to erroneous values. To address this problem, the thermal effects of the integrated sensor chip along with its packaging arising out of

C. RoyChaudhuri, S K Datta, H. Saha

International Journal on Smart Sensing and Intelligent Systems , ISSUE 3, 432–447

Research paper

0.35 μm CMOS OPTICAL SENSOR FOR AN INTEGRATED TRANSIMPEDANCE CIRCUIT

This paper presents an integrated optical receiver which consists of an integrated photodetector, and a transimpedance circuit. A series inductive peaking is used for enhancing the bandwidth. The proposed structure operates at a data rate of 10 Gb/s with a BER of 10-20 and was implemented in a 0.35 μm CMOS process. The integrated photodiode has a capacitance of 0.01 pF which permits to the structure to achieve a wide bandwidth (5.75 GHz) with only one inductor before the last stage; hence a

H. Escid, M. Attari, M. Ait aidir, W. Mechti

International Journal on Smart Sensing and Intelligent Systems , ISSUE 3, 467–481

Research Article

Implementation of 144 × 64 Pixel Array Bezel-Less Cmos Fingerprint Sensor

This paper proposes CMOS integrated 144 × 64 pixel array fingerprint sensor without a bezel electrode. In this paper, the architecture of CMOS capacitive fingerprint sensor readout circuit is presented for general type of a switched capacitive integrator scheme. The pipelined scan driver is included in the fingerprint sensor for fast image capture. It is implemented on 0.35 μm standard CMOS process technology. The operation is validated by SPECTRE for one-pixel and RTL simulation including

Seungmin Jung

International Journal on Smart Sensing and Intelligent Systems , ISSUE 1, 1–5

Research Article

DESIGN OF LOW COMPLEXITY ACCUMULATOR USING FINFET FOR VARIOUS TECHNOLOGIES

FINFET terminological in exactitude process reuses a massive part of well accustomed conventional CMOS process. FINFET is a likely-look alternative to conventional MOSFET which has reached its limit and has too much leakage for too little performance gain. FINFET is being suggested as basics for future IC processes because its power or performance benefits, scalability, superior controls over short channel effort etc., In this paper we propose a outlook for scheming accumulator using FINFET for

N. Sathya, Dr.M.Anto Bennet, M. Mageswari, M. Priya, M. Kayalvizhi

International Journal on Smart Sensing and Intelligent Systems , ISSUE 5, 225–235

Research Article

Nanocrystalline ZnO based MEMS Gas Sensors with CMOS ASIC for Mining Applications

transmitting the output of the gas sensor, a voltage controlled oscillator (VCO) chip integrated with a low noise amplifier has been fabricated in 0.35μm CMOS technology to convert the voltage output of the gas sensor to desirable frequency. The power consumption of the chip has been obtained to be around 3mW. The amplifier gain is set suitably ~13 to apply the desirable control voltage (~1.2V-3.2V)to the VCO. The noise of the amplifier has been obtained to be around 2μV/Hz1/2. The output frequency of the

N.P Futane, P. Bhattacharyya, S. Barma, C. Roychaudhuri, H. Saha

International Journal on Smart Sensing and Intelligent Systems , ISSUE 2, 430–442

Research Article

DESIGN OF LOW LEAKAGE CURRENT AVERAGE POWER CMOS CURRENT COMPARATOR USING SVL TECHNIQUE WITH PSEUDO NMOS AND TRANSMISSION GATE LOGICS

consumption from 258.6μw to 156.7μw. Pseudo nmos logic and transmission gate logic is used with the SVL based current comparator which further reduce the power consumption in the standby mode. This technique based comparator is fabricated on the tanner tool of 45nm technology.SVL technique is mostly recommended for CMOS logic.

T.R. Dinesh Kumar, K.Mohana Sundaram, M.Anto Bennet, M. Pooja, A.P. Kokila

International Journal on Smart Sensing and Intelligent Systems , ISSUE 5, 344–357

research-article

Touch fingerprint sensor based on sensor cell isolation technique with pseudo direct signaling

form large capacitances between the electrode and a finger to deliver sensor’s driver signal effectively. And the isolation scheme of the sensor cells prevents the unwanted signal inflows to the sensor cell in order to provide the stable evaluation of the capacitance formed between the sensor cell and fingerprint (Yeo, 2016). The fingerprint sensor with pseudo-direct signaling scheme was implemented and fabricated using 0.25 μm CMOS technology. The fingerprint sensor was molded with 80 μm-thick

Hyeopgoo Yeo

International Journal on Smart Sensing and Intelligent Systems , ISSUE 1, 1–9

Research Article

DESIGN OF LOW POWER CARRY SKIP ADDER USING DTCMOS

dynamic threshold complementary metal oxide semiconductor (DTCMOS).Tthe circuit is designed using tanner EDA simulator of 32nm technology. Also the circuit is compared with the CMOS technology methods.

T.R.Dinesh Kumar, K.Mohana Sundaram, M.Anto Bennet, Aruna .R, Meena .B, M. Mohanapriya

International Journal on Smart Sensing and Intelligent Systems , ISSUE 5, 284–294

Research Article

PREDISTORTION SYSTEM IMPLEMENTATION BASED ON ANALOG NEURAL NETWORKS FOR LINEARIZING HIGH POWER AMPLIFIERS TRANSFER CHARACTERISTICS

In order to correct non-linearities due to High Power Amplifiers (HPA) operating near saturation in telecommunication transceivers, a new adaptive predistortion system based on analog Neural Networks (NNs) was developed. Based on size, consumption and bandwidth considerations, Multi-Layer Perceptron (MLP) type NNs were implemented in a 0.6 μm CMOS ASIC. The NNs parameters are digitally updated with a computer, depending on simulation conditions (temperature drifts, ageing variations). The

B. Mulliez, E. Moutaye, H. Tap, L Gatet, F. Gizard

International Journal on Smart Sensing and Intelligent Systems , ISSUE 1, 400–420

Research Article

SIGNAL SENSING BY THE ARCHITECTURE OF EMBEDDED I/O PAD CIRCUITS

In this study, the detecting structures in an embedded CUP wafer, which are called sensors,are investigated through a contactless sensing analysis. These novel sensing structures, which were designed using the ADS 2009 platform and the design rules for the TSMC 0.18-μm CMOS process, were placed under bonding pads. However, signals would still pass through these I/O sensing structures (i.e., ESD devices or circuits) and become coupled up to the pads of the top-layer metal as square, sinusoidal

Shen-Li Chen, Yang-Shiung Cheng

International Journal on Smart Sensing and Intelligent Systems , ISSUE 1, 196–213

Research Article

FPGA-Based Implementation of Real Time Optical Flow Algorithm and Its Applications for Digital Image Stabilization

possible to reduce the computational complexity of the algorithm without compromising the processing accuracy. Both the accuracy and the limitations resulting from the introduced simplifications have been verified based on several examples of both synthetic and real movie samples. The presented algorithm has been implemented using VirtexII-1000 FPGA to realize a digital stabilization system for the CMOS camera images. Experimental results fully confirm the efficiency of the presented algorithm when

Robert Piotrowski, Stanislaw Szczepanski, Slawomir Koziel

International Journal on Smart Sensing and Intelligent Systems , ISSUE 2, 253–272

Research Article

Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors

implementation methodology ensure substantial reduction of propagation delay in comparison with Wallace Tree (WTM), modified Booth Algorithm (MBA), Baugh Wooley (BWM) and Row Bypassing and Parallel Architecture (RBPA) based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the

P. Saha, A. Banerjee, A. Dandapat, P. Bhattacharyya

International Journal on Smart Sensing and Intelligent Systems , ISSUE 2, 268–284

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