Article | 01-April-2018
This paper presents a fast CCD optical spectrum data acquisition method based on FPGA, FIFO and DSP. Introduces a linear CCD timing sequence control signal generation and high speed ADC interface with FIFO and DSP in detail, publishes this design key parts FPGA logic schematic and VHDL source code, provides a general solution for universal high speed CCD optical spectrum data acquisition and analysis system.
International Journal of Advanced Network, Monitoring and Controls, Volume 1 , ISSUE 1, –
research-article | 30-November-2020
certain threshold defined for the network or application, i.e.
. When the buffer queue length
, the packets arriving later are dropped. The model uses the first-in-first-out (FIFO) queue discipline for the transmission of the packets. When there is a requirement of service with priority, the packet is placed at the head of the queue or thereafter, if the head of the queue is also a priority packet. The queuing delay
International Journal on Smart Sensing and Intelligent Systems, Volume 14 , ISSUE 1, 1–6